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[Crack Hack] CRC

Description: 通过对于模2除法的研究 可以得到如下方法： 1． 把信息码后面加上p－1位的0，这个试验中p是6位，即在输入的信息码后面加上“00000”。把这个17位的被除数放入input中。 2． 在得到被除数input之后，设计一个在被除数上移动的数据滑块变量d，把input中的最高位开始逐次复制给变量d。 3． 如果d的最高位为1，由变量d和变量p做异或运算；如果d的最高位为0则不运算或者做多余的异或‘0’的运算。 4． 把滑块变量d往后滑动一位。 5． 循环步骤（3，4）11次。 6． 执行步骤3。 7． 得到余数c，把c转成信号输出。 -Through the 2-mode research division will be as follows: 1. Information code followed by the p-1-bit 0, this test p is 6, that is, the information in the input code after 00000. This 17 Add input in the dividend. 2. After receiving input dividend, dividend on the design of a mobile data slider variable d, the highest input in the beginning of successive copied to the variable d. 3. If the highest d for 1, by the variable d and variable p do XOR operations if d the highest computing to 0 or do not redundant XOR 0 arithmetic. 4. The slider sliding variable d next one. 5. Cycle of steps (3,4) 11. 6. Steps 3.7. Be more than a few c, the c into the output signal.
Platform: | Size: 6144 | Author: lijq | Hits:

[Crack Hack] mulf2m

Description: 椭圆曲线加密算法中的乘法器的生成，主要功能是实现在素域上的多项式模P(大素数）乘的运算。-Elliptic curve encryption algorithm to generate the multiplier, the main function is to achieve in the Su-domain polynomial module P (large prime numbers) by the operator.
Platform: | Size: 1024 | Author: 傅建新 | Hits:

[VHDL-FPGA-Verilog] 745221frequency

Description: 用Verilog HDL / VHDL实现的数字频率计（完整实验报告）-Using Verilog HDL/VHDL realization of digital frequency meter (complete test report)
Platform: | Size: 145408 | Author: 倪亮 | Hits:

[VHDL-FPGA-Verilog] VHDL_Development_Board_Sources

Description: CPLD开发板VHDL源程序并附上开发板的原理图-CPLD development board VHDL source code along with the development board schematics
Platform: | Size: 4709376 | Author: liaoyintang | Hits:

[VHDL-FPGA-Verilog] ECCgenAndLoc

Description: 基于xilinx ISE环境开发的VHDL的NAND flash ECC 实现,eccGen256Byte 文件夹为ECC 产生程序，EccErrLoc文件夹为ECC错误定位程序。-Xilinx ISE environment based on the development of VHDL the NAND flash ECC to achieve, eccGen256Byte folder produced for the ECC procedures, EccErrLoc folder location for the ECC error procedures.
Platform: | Size: 1504256 | Author: 卓智海 | Hits:

[VHDL-FPGA-Verilog] ppm

Description: ppm编码，本程序为编码的硬件语言的实现，包含测试文件，同时编译便可出结果-ppm coding procedures for the encoding of the language of the hardware implementation, including test papers, the results will be compiled at the same time
Platform: | Size: 2048 | Author: lu xin | Hits:

[VHDL-FPGA-Verilog] ThetaxiaccountingsystembasedonVHDL

Description: 利用VHDL 语言设计出租车计费系统, 使其实现计费以及预置和模拟汽车启动、停止、暂停等功能, 并设计动态扫描电路显示车费数目, 突出了其作为硬件描述语言的良好的可读性、可移植性和易理解等优点。此程序通过下载到特定芯片后, 可应用于实际的出租车计费系统中。-The taxi accounting system based on VHDL includes the design of the tariff software , the p reset and simulation ofthe car′s functions such as start, stop, pause and so on1 It displays the tariff number through the dynamic scanning circuit1 Thedesign of this system has show n the readability, portability and easily understanding of VHDL as a hard describe language1 The program can be used in the truly taxi accounting system by downloading to the given chip
Platform: | Size: 117760 | Author: 珍子 | Hits:

[Documents] TurbojiaozhiVHDL

Description: 一种基于turbo码的交织器设计，运用vhdl语言。-something about turbo。
Platform: | Size: 117760 | Author: xixi | Hits:

[VHDL-FPGA-Verilog] leijiaqi

Description: 累加器，一个加法器和一个寄存器构成的累加器，其用途是用于DDS技术的相位累加器 -ACC
Platform: | Size: 17408 | Author: 陈兴文 | Hits:

[Software Engineering] dso

Description: 使用VHDL语言编写的简易数字存储示波器，用MAX+PlusII仿真验证。VHDL编写了采样、存储写、存储读和显示4个模块。采样使用ADC0809，存储器使用6264，显示使用DAC0832。-The design of the chip as a high-speed signal ADC0809 the A/D converter, SRAM6264 memory for data storage after sampling, DAC0832 chip as a signal of D/A conversion. Programming using ultra-high-speed hardware description language VHDL description of its A/D conversion, A/D sampling controller and data storage, digital output programming, simulation, the completion of the design of hardware and software, as well as some of the experimental prototype debugging
Platform: | Size: 502784 | Author: 兰江营 | Hits:

[Crack Hack] BasicRSA_latest.tar

Description: RSA ( Rivest Shamir Adleman )is crypthograph system that used to give a secret information and digital signature . Its security based on Integer Factorization Problem (IFP). RSA uses an asymetric key. RSA was created by Rivest, Shamir, and Adleman in 1977. Every user have a pair of key, public key and private key. Public key (e) . You may choose any number for e with these requirements, 1< e <Æ (n), where Æ (n)= (p-1) (q-1) ( p and q are first-rate), gcd (e,Æ (n))=1 (gcd= greatest common divisor). Private key (d). d=(1/e) mod(Æ (n)) Encyption (C) . C=Mª mod(n), a = e (public key), n=pq Descryption (D) . D=C° mod(n), o = d (private key- RSA ( Rivest Shamir Adleman )is crypthograph system that used to give a secret information and digital signature . Its security based on Integer Factorization Problem (IFP). RSA uses an asymetric key. RSA was created by Rivest, Shamir, and Adleman in 1977. Every user have a pair of key, public key and private key. Public key (e) . You may choose any number for e with these requirements, 1< e <Æ (n), where Æ (n)= (p-1) (q-1) ( p and q are first-rate), gcd (e,Æ (n))=1 (gcd= greatest common divisor). Private key (d). d=(1/e) mod(Æ (n)) Encyption (C) . C=Mª mod(n), a = e (public key), n=pq Descryption (D) . D=C° mod(n), o = d (private key
Platform: | Size: 5120 | Author: nb | Hits:

[VHDL-FPGA-Verilog] PWM

Description: 实现PWM波的产生,可用于电机控制.可以改变其占空比及频率来实现电机的调速.-Realization of PWM wave generation, can be used for motor control. Can change its duty cycle and frequency to achieve the speed control motor.
Platform: | Size: 436224 | Author: 宋瑞鹏 | Hits:

[VHDL-FPGA-Verilog] Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_E

Description: Example VHDL project showing how to use a PWM by CPLD
Platform: | Size: 290816 | Author: maros | Hits:

[VHDL-FPGA-Verilog] audio_codec

Description: i2s协议时飞利浦公司专门为开发音频而开发的协议，这是它的VHDL代码，希望有帮助-i2s agreement, Philips developed specifically for the development of the audio protocol, which is its VHDL code, and want to help
Platform: | Size: 1742848 | Author: 王涛 | Hits:

[VHDL-FPGA-Verilog] VHDL_TP3067_PCM

Description: 用VHDL写的控制TP3067实现PCM编译码程序 包括系统原理图，VHDL源程序,各部分电路仿真。及完整的课程设计报告 -To use VHDL to write the control of TP3067 to achieve PCM encoding and decoding procedures, including system schematic, VHDL source code, the part of the circuit simulation. And complete report on curriculum design
Platform: | Size: 3392512 | Author: | Hits:

[Other] FFT

Description: IP核！！高速傅立叶变换的VHDL源代码 可以综合-IP core! ! High-speed Fourier transform of the VHDL source code can be integrated!!
Platform: | Size: 31744 | Author: 殷桃 | Hits:

[VHDL-FPGA-Verilog] VCO_WITH_PLL

Description: Voltage controlled oscillator with p-Voltage controlled oscillator with pll
Platform: | Size: 2048 | Author: sai | Hits:

[Other] VHDL

Description: 数字信号处理的FPGA实现,包括滤波器和DTF，FTT原理-FPGA realization of digital signal processing, including filters and DTF, FTT principle of
Platform: | Size: 182272 | Author: wlcwjy | Hits:

[Mathimatics-Numerical algorithms] fir_filter

Description: 该数字滤波器通过结合matlab和vhdl来实现低通fir数字滤波器功能-The digital filter through a combination of matlab and vhdl to achieve low-pass digital filter function fir
Platform: | Size: 26624 | Author: caoge | Hits:

[VHDL-FPGA-Verilog] DE2_user_manual_cn.pdf

Description: altera de2中文手册:de2提供了实用altera cyclone 2开发高级数字产品需要的所有模块.此为对应用户指南,在30分钟里面,可以浏览许多参考设计.-de2 user manual
Platform: | Size: 5166080 | Author: jl | Hits:
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